The trend in design and manufacturing of very large scale integrated circuit shows an ongoing move towards smaller devices on increasing wafer dimensions. CMOS has become the prevailing technology due to its high speed and packing density coupled with low power consumption. New technologies have emerged to further increase circuit speed and to reduce design and technology constraints. Examples are combined bipolar-CMOS (BICMOS) and CMOS in silicon on insulator (SOI). Besides the mass produced standard chips custom tailored application specific IC (ASICs) and system approaches with on chip integrated sensors or high power actuators gain importance. These developments pose challenges on the advancement of beam testing methods, e.g. high speed or high spatial resolution on 200 mm diameter wafers.